1. Field of the Invention
The present invention relates to a liquid crystal display device, and more particularly to a liquid crystal display device with a high aperture ratio having pixel electrodes overlapped with signal wiring that is capable of speeding up the data charging time of liquid crystal pixel cells. The present invention also is directed to a method of fabricating such a liquid crystal display device.
2. Discussion of the Related Art
Generally, an active matrix liquid crystal display (LCD) driving system displays a natural moving picture by employing thin film transistors (TFTs) as a switching device. Such a liquid crystal display has been commercially available for a monitor for a portable television and a lap-top type personal computer, etc. because it is easy to make a monitor having a smaller scale than the cathode ray tube or the Brown tube.
The active matrix LCD displays a picture corresponding to video signals such television signals on a pixel (or picture element) matrix having pixels arranged at each intersection between gate lines and data lines. Each pixel includes a liquid crystal cell for controlling the transmitted light quantity depending on a voltage level of a data signal from the data line. The TFT is formed at an intersection between the gate line and the data line and responds to a scanning signal (or gate pulse) from the gate line to thereby switch a data signal to be transmitted to the liquid crystal cell.
Typically, as shown in FIG. 1, the LCD has a TFT 30 formed at an intersection between a data line 22 and a gate line 24, and has pixel electrodes 20 arranged in a matrix pattern at a pixel area between the data line 22 and the gate line 24. The TFT 30 is formed on a transparent substrate 2 as shown in FIG. 2. The TFT 30 includes a gate electrode 4 connected to the gate line 24, a drain electrode 14 connected to the data line 22, and a source electrode 16 connected to the pixel electrode 20. A gate insulating film 6 made from an inorganic dielectric material such as SiNx is deposited on the entire transparent substrate 2 patterned with the gate electrode 4. On the gate insulating film 6, a semiconductor layer 8 made from amorphous silicon, hereinafter referred to as “a-Si”, and an Ohmic contact layer 10 made from a-Si doped with n+ ions are sequentially formed to cover the gate insulating film 6 on the gate electrode 4. The drain electrode 14 and the source electrode 16 made from a metal each are formed on the Ohmic contact layer 10. The drain electrode 14 and the source electrode 16 are patterned in such a manner to be spaced by a predetermined channel width. Then, the Ohmic contact layer 10 is etched along a channel formed between the drain source 14 and the source electrode 16 to expose the semiconductor layer 8. A protective film 18 made from SiNx or SiOx, etc. is deposited on the entire transparent substrate 2 to cover the TFT. The protective film 18 on the source electrode 16 is removed by etching to define a contact hole 12. The pixel electrode 20 made from Indium Tin Oxide is deposited in such a manner as to be connected to the source electrode 16 through the contact hole 12.
In the LCD as shown in FIG. 1, the pixel electrode 20 is patterned to make a distance of about 5 to 10 μm from the gate line 24. Also, a black matrix (not shown) is overlapped, by about 5 to 10 μm, with the pixel electrode 20. Thus, the LCD has an aperture ratio of about 50%. Accordingly, the LCD has low picture brightness as well as a large power consumed in the back light.
In order to improve an aperture ratio of the LCD, a scheme for allowing a pixel electrode to be overlapped with a gate line and a data line has been disclosed in U.S. Pat. No. 5,055,899. The LCD in the aforementioned patent uses an organic insulating film as a protective film 28 as shown in FIG. 3. This organic protective film 28 has its surface coated evenly by the spin coating technique into a thickness of 2000 to 8000 Å (or 0.2 to 0.8 μm). But the organic protective film 28 has a problem in that it generates a high parasitic capacitance at an overlapping area between the pixel electrode 20 and the data line 22, or the pixel electrode 20 and the gate electrode 24 because its thickness is small. Such a problem will be described in detail in conjunction with the following formula:                     C        =                              (                          ɛ              ⁢                                                          ⁢                              ɛ                0                            ⁢              A                        )                    d                                    (        1        )            wherein ε represents a dielectric constant of the organic protective film 28, and ε0 is 8.85×10−14 F/cm. “A” represents an overlapping area between the pixel electrode 20 and the data line 22 or the pixel electrode 20 and the gate line 24, and “d” denotes a thickness of the organic protective film 28. As the thickness of the organic protective film 28 is very low to be about 0.2 to 0.8 μm as described above, a parasitic capacitance generated by the overlapping area in the pixel electrode 20 is increased to that extent. As a parasitic capacitance value caused by the overlapping area in the pixel electrode 20 increases as described above, a capacitance value at the data line 22 or the gate line 24 is enlarged. Since the parasitic capacitance having such a large value enlarges a delay value of a signal applied from the data line 22 or the gate line 24, the liquid crystal cells fails to charge video signals sufficiently within a limited charge time. As a result, a picture is distorted such that a desired color signal can not be expressed.
Meanwhile, since the protective film 18 in the LCD as shown in FIG. 1 is made from an inorganic material such SiNx having a dielectric constant (ε) of about 6.7, or SiO2 having a dielectric constant (ε) of about 3.9, etc., it generates a very large parasitic capacitance when the pixel electrode 20 is overlapped with the data line 22 and the gate line 24 with the protective film 18 therebetween. As a result, in the LCD using an inorganic material as the protective film 18, the pixel electrode 20 cannot be overlapped with the data line 22 or the gate line 24.
In order to limit a parasitic capacitance caused by the overlapping area, U.S. Pat. No. 5,920,084 has suggested an appropriate thickness and dielectric constant of the organic protective film. In the aforementioned patent, a thickness of the organic protective film 28 was set to be more than 1.5 μm (preferably 2 to 3 μm). A dielectric constant of the organic protective film 28 was set to be less than 3.0. If the organic protective film 28 is set to have a high thickness and a low dielectric constant thereof, then a parasitic capacitance caused by the overlapping area is decreased as indicated in the above formula (1).
However, a rotation speed (RPM) at the time of the spin coating is lowered when a thickness of the organic protective film 28 is high, so that coating non-uniformity in the organic insulating film is increased and the evenness therein is deteriorated. Accordingly, a thickness recovery of the organic protective film 28 may be not only weakened, but also a residual of the organic protective film 28 may be left within the contact hole 32 for contacting the pixel electrode 20 with the source electrode 16 during the dry etching, or the source electrode 16 may be damaged or open-circuited due to the over etching. As a result, a contact resistance is increased or an open-circuit defect is generated between the pixel electrode 20 and the source electrode 16. Also, if a thickness of the organic protective film 28 becomes high, then a photoresist masked on the organic protective film 28 is thickened to that extent so as to protect the organic protective film 28 during the dry etching and a thickness non-uniformity in the photoresist is increased. For instance, when a thickness of the organic protective film 28 made from Benzocyclobutene (BCB) is 1.5 μm and a thickness of the gate insulating film 6 is 0.6 μm, a thickness of the photoresist is about 2.4 μm. A thickness uniformity in the photo resist can be assured when a thickness of the photoresist is less than 2.5 μm, but it is difficult to form a thickness of the photoresist uniformly when a thickness of the photoresist is more than 2.5 μm. Also, if a thickness of the photoresist becomes high, then a time required for the etching, the exposure and the development during the dry etching is increased to that extent to thereby reduce the productivity.